One of the best lab classes in UCD. Verilog is not intuitive and has mountains of documentation. Just search how to do things. Akella gives many many examples of code in lecture. So you should scarcely have any problems with the labs.

Verilog modelling of combinational and sequential circuits. Timing analysis. Brief coverage of CMOS implementation. Very useful stuff.

He cares a lot about his students and their ability to learn. He is happy to see you outside of class, and he extends his office hours too.

Make sure you do computer architecture (EEC 170) before this class, because it will help you build a nice project.

Yeah this course was pretty terrible, mainly because of the professor. The actual subject matter was interesting and useful to learn so it's like, go try to learn an important skill for your major, but with an awful professor.

Course is mainly on Verilog. The problem is that only really simple, basic stuff is taught, a lot of which is not even used in industry anymore. Would have been much better just to teach SystemVerilog since that's been the IEEE standard since the 2000s. SystemVerilog covers a lot of stuff, but teaching just the RTL part in that HDL would have been better.

Professor was awful. Information was pretty obsolete. Terrible at explaining, if you would call it that. I don't mind a hard professor, (trust me I took EEC112), but at least match that standard in his teaching. Labs are basically figure it out yourself or fail because you can't even get help on them. This is not what education and learning should be about. Even the labs weren't very practical.

Don't take this professor. If you do, don't work with other students otherwise you might get falsely accused of cheating (I heard many stories). Try your best, and you'll probably pass because he curves heavily in the end. I got an F simply because I refused to do work for such a bad professor. Looking back, I probably should have just gutted it out.

Anyone but this one.