Loved it.

Very. It’s required for EE but I think that it’s a useful skill for all CPe and cise too.

Dr Cheney used dr Stitts materials. He was super interested in the topics. Stitts lectures were great, and Dr Cheney was great to work with for issues and questions.

Study some basics of VHDL first. Or your first few weeks will be real hectic.

The class is super interesting and you get to learn a lot by DOING. I know for me that the class filled in the holes that were left for digital logic, but presented in a way that is more easily digestible. I have heard that people enjoy and understand VHDL a lot more after taking this class if you took Dr. Bobda's version of DL.

In this course, you will learn about VHDL code, which is a software language that allows you to essentially program hardware. That's not what is really happening under the hood, but for all intents and purposes, yes. You can create custom digital circuits by programming it and uploading it onto a Field Programmable Gate Array (FPGA). Additionally, this course will also teach you how to create state machines and data paths. In general, this class is a nice review and continuation of digital logic. So if you enjoyed the concepts and labs of DL but didn't like the stress, you will love this class. Note: I took DL with Dr. Schwartz two years ago, so keep the prof and timeframe in mind.

Dr. Stitt is an incredible professor. He's won many teaching awards specifically because he knows how to give students the opportunity to learn in a great environment. His notes, lectures, and labs are designed beautifully, and he is probably one of the best professors in the ECE department.

Do not procrastinate the final project. Dr. Stitt, in both of his classes, has labs that are easy-going and doable until the final project. Then it'll hit fast, hard, and you won't be able to get too much TA intervention. So start early!

It's a Stitt class about FPGAs. It was a driving force for me pursuing FPGA design, and I would recommend it to anyone seeking out the field.

RTL design for FPGA work in VHDL using Quartus and Modelsim. Final project was designing a MIPS processor structurally. He makes it look easy.

He likes his FPGAs, and his instruction sure does show it. He walks you through so many pitfalls that I can't even count.

You can search Stitt's slides and labs from previous semesters on his website.

Stitt

Fairly easy until the last third or so. Instructor tried having us do labs over thanksgiving break. Last two projects can be very complex.

Learning to code in a HDL is a fairly important skill. Will gain knowledge of computer architecture, but wish they covered pipelining.

Avoid professor if you can. Fairly new so class became very disorganized. Not very good at teaching.

Stitt